(1) Field of the Invention
The invention relates to a process for making self-aligned field emitter devices and the resulting devices which can be used for various applications including flat panel displays, electron sources for lithography and the like, memory writing devices, sensors and high speed switching device.
(2) Description of the Prior Art
U.S. Pat. No. 4,763,187 to J. P. Biberian generally discusses field emission device structures including tips emitting electrons to light a fluorescent screen, using lines and columns for addressing. The structure includes a grid, at a third voltage potential (the first two potentials being those of the cathode and anode) which is used to control electron emission intensity. Biberian says that the grid solves the problem of needing low voltage levels (to allow for fast switching) but without requiring very small spacing, on the order of a few microns, between the tips and the anode structure. A few micron spacing would cause great difficulty in manufacturing. His structure using the grid also allows for the separate control of the address and intensity functions.
Another matrix addressed flat panel display is shown in U.S. Pat. No. 4,857,799 by C. A. Spindt et al. He refers to U.S. Pat. No. 3,500,102 by Crost et al which deals with a thin display using field emission, but which did not deal with gaseous breakdown, and which would still have a problem of distortion in the display picture, due to screen deflection from pressure difference between atmospheric pressure and vacuum inside display. Solutions to this problem proposed by Spindt et al included: 1) a "support structure" to prevent the distortion, 2) spacing between the cathodes and luminescent material which is less than or equal to the mean free path of electron in the interelectrode space--this would help reduce gas breakdown, and 3) isolating the cathode conductive lines by using semiconductive material between the conductive lines, to reduce cross-talk.
The U.S. Pat. No. 4,857,161 to Borel et al shows a process for the production of an array of cathode lines and grid lines that are used to address each picture element. At each picture element there are many micro-emitters that are grown on the corresponding cathode line. The many micro-emitters provide redundancy, so that if one emitter fails, there is no degradation in the display.
There are several methods for fabricating the gated field emitters. One such process is taught by the Borel et al Patent of the previous paragraph. Another process uses a silicon oxide mask on a silicon wafer and the silicon is etched under the mask until a pointed silicon structure remains under the mask. Then the dielectric and conductor layer are deposited thereover and the "hat" removed. A third process forms the emitter tip first and then forms the dielectric and conductive layers thereover. An etchback is required to expose the emitter tip. This third method is shown for example in U.S. Pat. No. 5,186,670 to Doan et al. Other methods for fabricating gated field emitter include those shown in U.S. Pat. Nos. 5,151,061 to Sandhu and 5,188,977 to Stengl et al.
The FIGS. 1 through 4 illustrate how Borel et al fabricates their gated field emitter. Typically a silicon wafer 10 is used as the substrate. A dielectric layer 12, such as silicon oxide is formed over the wafer 10. A conducting coating 14 is formed over the dielectric layer 12. Thereafter, using lithography and etching techniques openings 15 are formed through the conducting layer 14 and dielectric layer 12 to the silicon wafer 10 to produce FIG. 1. A lift off layer 18, which could be composed of nickel, aluminum, aluminum oxide or the like is formed over the layer 14 at a low angle to prevent deposit within the hole 15 to produce FIG. 2. Molybdenum or the like is deposited under normal incidence to form cone 16 within the openings and layer 20 on the surface of the lift off layer 18 as can be seen in FIG. 3. The gated field emitter is completed as seen in FIG. 4, with the lift off of the layer 20 by selectively dissolving the layer 18.
All of the above mentioned fabrication process for gated field emitters have serious drawbacks. The Borel et al process has several serious problems including (1) the lift off of the layer 20 by means of lift off layer 18 is a big problem, (2) the gate opening reduction is very limited and therefor operation voltages are limited to a high range of the order of 80 to 100 volts, and (3) the formation of the lift off layer 18 requires a very low angle deposition to prevent any of the material from entering the openings 15. The "hat" method has many problems including (1) some of the "hats" fall off during etching causing reliability problems, (2) gate opening reduction is limited and therefor will be limited to high voltage operation in the order of 80 to 100 volts and (3) only silicon and tantalum have been reported as material candidates for emitter. The third method of Doan et al has many problems which include (1) the gate cannot be made planer and (2) the device has a high capacitance and high leakage current, since dielectric thickness cannot be thick in order to have the necessary gate opening size.
It is a principal object of the invention to provide a simple and very manufacturable method for making self-aligned gated field emitters in a planar structure, without limitation as to substrate material or emitter material, and without use of a lift off process step.
Another object is the formation of a gated field emitter device which is self-aligned to the gate and with the capability to reduce the gate opening, without limitation as to substrate material and without use of a lift off process step.